# 'Errors' using the minted VHDL environment

I recently started university, and was annoyed to find out, we had to do our reports and assignments in LaTeX... until I learned how to use it! I went from hating it to loving it in one day. :) But seeing as I'm still very new, I might have some noobish questions - so please forgive me...

Anyways, on to the question, I am trying to use the minted environment, to write some VHDL code inside. I am having two issues (though solving one, might solve the other...)

I have written the following code:

which results in the following:

So my problem is this: LaTeX (Minted?) doesn't recognize the "Signal" line. it puts red boxes around the commas and colon and from the coloring it seems it doesn't recognize the "std_logic" in this context... Any ideas how to solve this?

Please let me know if I need to specify the problem any further...

ps. what I'm hoping it will look like in the end, is this(minus the comments):

I hope this will suffice as a minimal example, though the preamble might be a bit too extensive - it does reproduce the problem (to me at least):

\documentclass[12pt,a4paper]{article}
\usepackage[utf8]{inputenc}
\usepackage[danish]{babel}
\usepackage{amsmath}
\usepackage{amsfonts}
\usepackage{amssymb}
\usepackage{graphicx}
\usepackage{color}
\usepackage{minted}

\begin{document}

\begin{minted}[obeytabs,linenos,firstnumber=1,frame=leftline]{vhdl}
LIBRARY iee;
USE ieee.std_logic_1164.all;

ENTITY func IS
PORT(A,B,C,D    :   IN STD_LOGIC;
X      :   OUT STD_LOGIC);
END func

ARCHITECTURE LogicFunc OF func IS
SIGNAL I,J,K,L  :    STD_LOGIC;
BEGIN
L <= C  XOR D;
I <= L  AND B;
J <= A  OR  B;
K <= I  AND J;
X <= A  OR  L;
END LogicFunc;
\end{minted}

\end{document}

• Can you post the code (not a screenshot, so that it can be copied) for a complete, short document that produces this? I can't reproduce the problem, at least retyping a couple of lines around your code line 10. So it's possible that there is a package conflict or some other issue that can't be found without looking at a complete, minimal example. – G. Poore Oct 21 '14 at 22:31
• @Joachim meta.tex.stackexchange.com/questions/228/…. Further doesn't the listings package give you a suitable output? It has markup support for VHDL... ftp.tex.ac.uk/tex-archive/macros/latex/contrib/listings/… – WG- Oct 21 '14 at 22:35
• I have updated my question with a minimal example. – Joachim Langtved Axelsen Oct 23 '14 at 11:40
• I have also tried the listings environment as you can see in my screenshot, but it it is my understanding, that using the minted package, I can get a much better looking code example, as it actually looks like what it would look like in the actual coding environment... As far as I could get working, listings could color a very limited part of my code (only LIBRARY, ENTITY, END etc.) where as minted actually color the entire piece of code... very frustrating when it aaalmost works... Thank you very much for taking your time to try and answer :) – Joachim Langtved Axelsen Oct 23 '14 at 11:46
• I believe you need END func --> END func;. The missing semicolon is interfering with the highlighting. – G. Poore Oct 23 '14 at 13:20

You need END func --> END func;. The missing semicolon is interfering with the highlighting.