1

I've got a slight problem with my longtable using the IEEEtran article class.

I'm using something close to this MWE, the original one is 4-pages longer than this, and the MWE captures the problem. The \specialcell{} comes from this answer in the source below.

\documentclass[journal]{IEEEtran}
\usepackage{longtable,booktabs,multirow,lipsum,array}
\newcommand{\specialcell}[2][c]{%
  \begin{tabular}[#1]{@{}c@{}}#2\end{tabular}}

\title{A MWE with a longtable cell width problem}

\author{Joao Andrade}

\begin{document}
\maketitle

{\footnotesize\onecolumn
\begin{longtable}{c | cr | r | crrcc | c | c | rrr | c}

\caption{Summary of stuff.}
\label{tab:big_table_over_margins}\\
\multirow{1}{*}{Work} & \multicolumn{2}{c|}{Parallelism} & \multicolumn{1}{c|}{Data} & \multicolumn{5}{c|}{LDPC Code} & \multicolumn{2}{c|}{Decoding} & \multicolumn{3}{c|}{Perf.} & \multicolumn{1}{c}{Platform}\tabularnewline\midrule
%\cline{2-15} 
 & Thread- & Data- & \multicolumn{1}{c|}{Width} & \multicolumn{1}{c}{Code} & q & N & Rate & Tanner & Sched. & Alg. & \specialcell{Lat.\\(ms)} & \specialcell{Thr.\\(Mbit/s)} & Iter. & Name\tabularnewline
\midrule
\endfirsthead
\multicolumn{4}{c}%
{\tablename\ \thetable\ \textit{\centering Continued from previous page}} \\
\multirow{1}{*}{Work} & \multicolumn{2}{c|}{Parallelism} & \multicolumn{1}{c|}{Data} & \multicolumn{5}{c|}{LDPC Code} & \multicolumn{2}{c|}{Decoding} & \multicolumn{3}{c|}{Perf.} & \multicolumn{1}{c}{Platform}\tabularnewline\midrule
 & Thread- & Data- & \multicolumn{1}{c|}{Width} & \multicolumn{1}{c}{Code} & q & N & Rate & Tanner & Sched. & Alg. & \specialcell{Latency \\(ms)} & \specialcell{Thr.\\(Mbit/s)} & Iter. & Name\tabularnewline
\midrule

\endhead
\midrule \multicolumn{4}{r}{\textit{Continued on next page}} \\
\endfoot
\endlastfoot 

\multirow{5}{*}{Work 1} & \multirow{5}{*}{{bpc}} & \multirow{3}{*}{512} & \multirow{5}{*}{6--8} & \multirow{5}{*}{802.16e} & \multirow{5}{*}{2} & 768 & \multirow{5}{*}{1/2} & \multirow{5}{*}{Struct.} & \multirow{5}{*}{TDMP} & \multirow{5}{*}{MSA} & 2.62 & 150 & \multirow{5}{*}{10} & \multirow{5}{*}{\specialcell{GeForce\\9800 GTX+}}\tabularnewline
 &  &  &  &  &  & 1152 &  &  &  &  & 3.88  & 152 &  & \tabularnewline
 &  &  &  &  &  & 1536 &  &  &  &  & 4.91 & 160 &  & \tabularnewline
 &  & 384 &  &  &  & 1920 &  &  &  &  & 5.27 & 140 &  & \tabularnewline
 &  & 256 &  &  &  & 2304 &  &  &  &  & 3.69 & 160 &  & \tabularnewline
Work 2 & {cpc} & 128 & 8 & 802.16e & 2 & 2304 & 1/2 & Struct. & TDMP & MSA & 1.09 & 270 & 10 & \specialcell{Cell\\B.E.}\tabularnewline
\hline
 \multirow{4}{*}{Work 3} & \multirow{4}{*}{{tpn}} & \multirow{4}{*}{1} & \multirow{4}{*}{8} & \multirow{4}{*}{802.16e} &  & 768 & \multirow{4}{*}{1/2} & \multirow{4}{*}{Struct.} & \multirow{4}{*}{TPMP} & \multirow{4}{*}{MSA} & 0.01 & 98.7 & \multirow{4}{*}{10} & \multirow{4}{*}{\specialcell{Nallatech\\PCI 385N D5}}\tabularnewline
  &  &  &  &  &  & 1152 &  &  &  &  & 0.01 & 103.9 &  & \tabularnewline
  &  &  &  &  &  & 1536 &  &  &  &  & 0.02 & 81.4 &  & \tabularnewline
  &  &  &  &  &  & 1920 &  &  &  &  & 0.02 & 81.0 &  & \tabularnewline
 \multirow{4}{*}{Work 4} & \multirow{4}{*}{bpe} & \multirow{4}{*}{4} & \multirow{4}{*}{32} & \multirow{4}{*}{Regular} & 32 & \multirow{4}{*}{384} & \multirow{4}{*}{1/3} & \multirow{4}{*}{Sparse} & \multirow{4}{*}{TPMP} & \multirow{4}{*}{\specialcell{FFT-\\-SPA}} & 14.93 & 0.82 & \multirow{4}{*}{10} & \multirow{4}{*}{\specialcell{Tesla\\C1060}}\tabularnewline
  &  &  &  &  & 64 &  &  &  &  &  & 31.55 & 0.39 &  & \tabularnewline
 &  &  &  &  & 128 &  &  &  &  &  & 7.36 & 1.67 &  & \tabularnewline
  &  &  &  &  & 256 &  &  &  &  &  & 10.28 & 1.20 &  & \tabularnewline
 \hline 
 \multirow{6}{*}{Work 5} & \multirow{2}{*}{{tpn}} & \multirow{6}{*}{1} & \multirow{6}{*}{8} & \multirow{2}{*}{802.11n} & \multirow{6}{*}{2} & \multirow{2}{*}{1944} & \multirow{2}{*}{1/2} & \multirow{2}{*}{Struct.} & \multirow{2}{*}{TPMP} & \multirow{2}{*}{MSA} & 0.12 & 16 & \multirow{6}{*}{10} & \multirow{2}{*}{\specialcell{Nallatech\\PCI 385N D5}}\tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.09 & 21 &  & \tabularnewline
  & \multirow{4}{*}{N/A} &  &  & \multirow{4}{*}{DVB-S2} &  & \multirow{4}{*}{64800} & \multirow{4}{*}{1/2} & \multirow{4}{*}{Struct.} & \multirow{4}{*}{\specialcell{TPMP\\TDMP}} & \multirow{4}{*}{MSA} & 0.28 & 234 &  & \multirow{2}{*}{\specialcell{Virtex5 LX330T\\Max2 Board}}\tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.05 & 1260 &  & \tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.28 & 234 &  & \multirow{2}{*}{\specialcell{Virtex6 LX330T\\Max3 Board}}\tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.05 & 1296 &  & \tabularnewline
 \bottomrule
\end{longtable}
\lipsum[1]



{\footnotesize\onecolumn
\begin{longtable}{@{}c@{} | @{}c@{}@{}r@{} | @{}r@{} | @{}c@{}@{}r@{}@{}r@{}@{}c@{}@{}c@{} | @{}c@{} | @{}c@{} | @{}r@{}@{}r@{}@{}r@{} | @{}c@{}}

\caption{Summary of stuff.}
\label{tab:big_table_nospace}\\
\multirow{1}{*}{Work} & \multicolumn{2}{c|}{Parallelism} & \multicolumn{1}{c|}{Data} & \multicolumn{5}{c|}{LDPC Code} & \multicolumn{2}{c|}{Decoding} & \multicolumn{3}{c|}{Perf.} & \multicolumn{1}{c}{Platform}\tabularnewline\midrule
%\cline{2-15} 
 & Thread- & Data- & \multicolumn{1}{c|}{Width} & \multicolumn{1}{c}{Code} & q & N & Rate & Tanner & Sched. & Alg. & \specialcell{Lat.\\(ms)} & \specialcell{Thr.\\(Mbit/s)} & Iter. & Name\tabularnewline
\midrule
\endfirsthead
\multicolumn{4}{c}%
{\tablename\ \thetable\ \textit{\centering Continued from previous page}} \\
\multirow{1}{*}{Work} & \multicolumn{2}{c|}{Parallelism} & \multicolumn{1}{c|}{Data} & \multicolumn{5}{c|}{LDPC Code} & \multicolumn{2}{c|}{Decoding} & \multicolumn{3}{c|}{Perf.} & \multicolumn{1}{c}{Platform}\tabularnewline\midrule
 & Thread- & Data- & \multicolumn{1}{c|}{Width} & \multicolumn{1}{c}{Code} & q & N & Rate & Tanner & Sched. & Alg. & \specialcell{Latency \\(ms)} & \specialcell{Thr.\\(Mbit/s)} & Iter. & Name\tabularnewline
\midrule

\endhead
\midrule \multicolumn{4}{r}{\textit{Continued on next page}} \\
\endfoot
\endlastfoot 

\multirow{5}{*}{Work 1} & \multirow{5}{*}{{bpc}} & \multirow{3}{*}{512} & \multirow{5}{*}{6--8} & \multirow{5}{*}{802.16e} & \multirow{5}{*}{2} & 768 & \multirow{5}{*}{1/2} & \multirow{5}{*}{Struct.} & \multirow{5}{*}{TDMP} & \multirow{5}{*}{MSA} & 2.62 & 150 & \multirow{5}{*}{10} & \multirow{5}{*}{\specialcell{GeForce\\9800 GTX+}}\tabularnewline
 &  &  &  &  &  & 1152 &  &  &  &  & 3.88  & 152 &  & \tabularnewline
 &  &  &  &  &  & 1536 &  &  &  &  & 4.91 & 160 &  & \tabularnewline
 &  & 384 &  &  &  & 1920 &  &  &  &  & 5.27 & 140 &  & \tabularnewline
 &  & 256 &  &  &  & 2304 &  &  &  &  & 3.69 & 160 &  & \tabularnewline
Work 2 & {cpc} & 128 & 8 & 802.16e & 2 & 2304 & 1/2 & Struct. & TDMP & MSA & 1.09 & 270 & 10 & \specialcell{Cell\\B.E.}\tabularnewline
\hline
 \multirow{4}{*}{Work 3} & \multirow{4}{*}{{tpn}} & \multirow{4}{*}{1} & \multirow{4}{*}{8} & \multirow{4}{*}{802.16e} &  & 768 & \multirow{4}{*}{1/2} & \multirow{4}{*}{Struct.} & \multirow{4}{*}{TPMP} & \multirow{4}{*}{MSA} & 0.01 & 98.7 & \multirow{4}{*}{10} & \multirow{4}{*}{\specialcell{Nallatech\\PCI 385N D5}}\tabularnewline
  &  &  &  &  &  & 1152 &  &  &  &  & 0.01 & 103.9 &  & \tabularnewline
  &  &  &  &  &  & 1536 &  &  &  &  & 0.02 & 81.4 &  & \tabularnewline
  &  &  &  &  &  & 1920 &  &  &  &  & 0.02 & 81.0 &  & \tabularnewline
 \multirow{4}{*}{Work 4} & \multirow{4}{*}{bpe} & \multirow{4}{*}{4} & \multirow{4}{*}{32} & \multirow{4}{*}{Regular} & 32 & \multirow{4}{*}{384} & \multirow{4}{*}{1/3} & \multirow{4}{*}{Sparse} & \multirow{4}{*}{TPMP} & \multirow{4}{*}{\specialcell{FFT-\\-SPA}} & 14.93 & 0.82 & \multirow{4}{*}{10} & \multirow{4}{*}{\specialcell{Tesla\\C1060}}\tabularnewline
  &  &  &  &  & 64 &  &  &  &  &  & 31.55 & 0.39 &  & \tabularnewline
 &  &  &  &  & 128 &  &  &  &  &  & 7.36 & 1.67 &  & \tabularnewline
  &  &  &  &  & 256 &  &  &  &  &  & 10.28 & 1.20 &  & \tabularnewline
 \hline 
 \multirow{6}{*}{Work 5} & \multirow{2}{*}{{tpn}} & \multirow{6}{*}{1} & \multirow{6}{*}{8} & \multirow{2}{*}{802.11n} & \multirow{6}{*}{2} & \multirow{2}{*}{1944} & \multirow{2}{*}{1/2} & \multirow{2}{*}{Struct.} & \multirow{2}{*}{TPMP} & \multirow{2}{*}{MSA} & 0.12 & 16 & \multirow{6}{*}{10} & \multirow{2}{*}{\specialcell{Nallatech\\PCI 385N D5}}\tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.09 & 21 &  & \tabularnewline
  & \multirow{4}{*}{N/A} &  &  & \multirow{4}{*}{DVB-S2} &  & \multirow{4}{*}{64800} & \multirow{4}{*}{1/2} & \multirow{4}{*}{Struct.} & \multirow{4}{*}{\specialcell{TPMP\\TDMP}} & \multirow{4}{*}{MSA} & 0.28 & 234 &  & \multirow{2}{*}{\specialcell{Virtex5 LX330T\\Max2 Board}}\tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.05 & 1260 &  & \tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.28 & 234 &  & \multirow{2}{*}{\specialcell{Virtex6 LX330T\\Max3 Board}}\tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.05 & 1296 &  & \tabularnewline
 \bottomrule
\end{longtable}
\lipsum[1]



{\footnotesize\onecolumn
\begin{longtable}{@{ }c@{ } | @{ }c@{ }@{ }r@{ } | @{ }r@{ } | @{ }c@{ }@{ }r@{ }@{ }r@{ }@{ }c@{ }@{ }c@{ } | @{ }c@{ } | @{ }c@{ } | @{ }r@{ }@{ }r@{ }@{ }r@{ } | @{ }c@{ }}

\caption{Summary of stuff.}
\label{tab:big_table_somespace}\\
\multirow{1}{*}{Work} & \multicolumn{2}{c|}{Parallelism} & \multicolumn{1}{c|}{Data} & \multicolumn{5}{c|}{LDPC Code} & \multicolumn{2}{c|}{Decoding} & \multicolumn{3}{c|}{Perf.} & \multicolumn{1}{c}{Platform}\tabularnewline\midrule
%\cline{2-15} 
 & Thread- & Data- & \multicolumn{1}{c|}{Width} & \multicolumn{1}{c}{Code} & q & N & Rate & Tanner & Sched. & Alg. & \specialcell{Lat.\\(ms)} & \specialcell{Thr.\\(Mbit/s)} & Iter. & Name\tabularnewline
\midrule
\endfirsthead
\multicolumn{4}{c}%
{\tablename\ \thetable\ \textit{\centering Continued from previous page}} \\
\multirow{1}{*}{Work} & \multicolumn{2}{c|}{Parallelism} & \multicolumn{1}{c|}{Data} & \multicolumn{5}{c|}{LDPC Code} & \multicolumn{2}{c|}{Decoding} & \multicolumn{3}{c|}{Perf.} & \multicolumn{1}{c}{Platform}\tabularnewline\midrule
 & Thread- & Data- & \multicolumn{1}{c|}{Width} & \multicolumn{1}{c}{Code} & q & N & Rate & Tanner & Sched. & Alg. & \specialcell{Latency \\(ms)} & \specialcell{Thr.\\(Mbit/s)} & Iter. & Name\tabularnewline
\midrule

\endhead
\midrule \multicolumn{4}{r}{\textit{Continued on next page}} \\
\endfoot
\endlastfoot 

\multirow{5}{*}{Work 1} & \multirow{5}{*}{{bpc}} & \multirow{3}{*}{512} & \multirow{5}{*}{6--8} & \multirow{5}{*}{802.16e} & \multirow{5}{*}{2} & 768 & \multirow{5}{*}{1/2} & \multirow{5}{*}{Struct.} & \multirow{5}{*}{TDMP} & \multirow{5}{*}{MSA} & 2.62 & 150 & \multirow{5}{*}{10} & \multirow{5}{*}{\specialcell{GeForce\\9800 GTX+}}\tabularnewline
 &  &  &  &  &  & 1152 &  &  &  &  & 3.88  & 152 &  & \tabularnewline
 &  &  &  &  &  & 1536 &  &  &  &  & 4.91 & 160 &  & \tabularnewline
 &  & 384 &  &  &  & 1920 &  &  &  &  & 5.27 & 140 &  & \tabularnewline
 &  & 256 &  &  &  & 2304 &  &  &  &  & 3.69 & 160 &  & \tabularnewline
Work 2 & {cpc} & 128 & 8 & 802.16e & 2 & 2304 & 1/2 & Struct. & TDMP & MSA & 1.09 & 270 & 10 & \specialcell{Cell\\B.E.}\tabularnewline
\hline
 \multirow{4}{*}{Work 3} & \multirow{4}{*}{{tpn}} & \multirow{4}{*}{1} & \multirow{4}{*}{8} & \multirow{4}{*}{802.16e} &  & 768 & \multirow{4}{*}{1/2} & \multirow{4}{*}{Struct.} & \multirow{4}{*}{TPMP} & \multirow{4}{*}{MSA} & 0.01 & 98.7 & \multirow{4}{*}{10} & \multirow{4}{*}{\specialcell{Nallatech\\PCI 385N D5}}\tabularnewline
  &  &  &  &  &  & 1152 &  &  &  &  & 0.01 & 103.9 &  & \tabularnewline
  &  &  &  &  &  & 1536 &  &  &  &  & 0.02 & 81.4 &  & \tabularnewline
  &  &  &  &  &  & 1920 &  &  &  &  & 0.02 & 81.0 &  & \tabularnewline
 \multirow{4}{*}{Work 4} & \multirow{4}{*}{bpe} & \multirow{4}{*}{4} & \multirow{4}{*}{32} & \multirow{4}{*}{Regular} & 32 & \multirow{4}{*}{384} & \multirow{4}{*}{1/3} & \multirow{4}{*}{Sparse} & \multirow{4}{*}{TPMP} & \multirow{4}{*}{\specialcell{FFT-\\-SPA}} & 14.93 & 0.82 & \multirow{4}{*}{10} & \multirow{4}{*}{\specialcell{Tesla\\C1060}}\tabularnewline
  &  &  &  &  & 64 &  &  &  &  &  & 31.55 & 0.39 &  & \tabularnewline
 &  &  &  &  & 128 &  &  &  &  &  & 7.36 & 1.67 &  & \tabularnewline
  &  &  &  &  & 256 &  &  &  &  &  & 10.28 & 1.20 &  & \tabularnewline
 \hline 
 \multirow{6}{*}{Work 5} & \multirow{2}{*}{{tpn}} & \multirow{6}{*}{1} & \multirow{6}{*}{8} & \multirow{2}{*}{802.11n} & \multirow{6}{*}{2} & \multirow{2}{*}{1944} & \multirow{2}{*}{1/2} & \multirow{2}{*}{Struct.} & \multirow{2}{*}{TPMP} & \multirow{2}{*}{MSA} & 0.12 & 16 & \multirow{6}{*}{10} & \multirow{2}{*}{\specialcell{Nallatech\\PCI 385N D5}}\tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.09 & 21 &  & \tabularnewline
  & \multirow{4}{*}{N/A} &  &  & \multirow{4}{*}{DVB-S2} &  & \multirow{4}{*}{64800} & \multirow{4}{*}{1/2} & \multirow{4}{*}{Struct.} & \multirow{4}{*}{\specialcell{TPMP\\TDMP}} & \multirow{4}{*}{MSA} & 0.28 & 234 &  & \multirow{2}{*}{\specialcell{Virtex5 LX330T\\Max2 Board}}\tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.05 & 1260 &  & \tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.28 & 234 &  & \multirow{2}{*}{\specialcell{Virtex6 LX330T\\Max3 Board}}\tabularnewline
  &  &  &  &  &  &  &  &  &  &  & 0.05 & 1296 &  & \tabularnewline
 \bottomrule
\end{longtable}
\lipsum[1]




\end{document}

The original paper comes in two-column, but margins remain the same under onecolumn so \lipsum[1] suffices to mark the limits to the longtable width.

The first table clearly outspans the margins margins. So I changed the spacing between text in each cell to @{} in \ref{tab:big_table_nospace}. The result stays within the margins with a problemno space. The fourth column is too wide for what it's supposed to be.

Making @{} to be @{ } in \ref{tab:big_table_some_space} sees similar issue. The fourth column is too wideenter image description here.

How does one solve this? It is clear that the table is one the brink of fitting to the margins. However, even with manually adjustment of the cells as p{.##cm} makes the fourth column to grow to be too wide. What am I missing here?

  • For start try to reduce tabcolsep to 4pt by \setlength{\tabcolsep}{4pt}. After than table will fit to width of text. However, to my test your table will still looks ugly. – Zarko Oct 7 '15 at 17:43
  • Yes, indeed it is an ugly table. That "does" the trick for keeping it within the margins. However, the fourth column is still oddly wide, no? Compare it with the first column, for instance. – Joao Andrade Oct 7 '15 at 17:56
2

Edit: I play a little with your table. In the first I add package makecell -- from it I use macros \multirowcell and thead -- and package siunitx for better formation the 13th column. With thead I replace defined command specilacell

Then I for shorter writing define three new commands: \mc for shorthand for \multicolumn, mrc as shorthand for multirowcell with centered cell's content and mrcR as shorthand for multirowcell with right aligned cell's content.

Beside those I erase vertical lines in table and reduce tabcolsep onto 4.5pt, change used font from footnotesize to \small. Horizontal line between first and second row I replace with series of \cmidrule .

On the end I clean-up your code. Obtained result is:

enter image description here

In MWE I also escape definitions for the second table head and for table foot. It should be easy add in sense as is defined the first head.

\documentclass[journal]{IEEEtran}
    \usepackage{array,booktabs,longtable,makecell,multirow}
\newcommand\mc[2]{\multicolumn{#1}{c}{#2}}
\newcommand\mrcR[2]{\multirowcell{#1}[0pt][r]{#2}}
\newcommand\mrc[2]{\multirowcell{#1}[0pt][c]{#2}}
    \usepackage{siunitx}

    \usepackage{lipsum}
%    \usepackage{showframe}

\begin{document}
    {\onecolumn
     \small
     \setlength{\tabcolsep}{4.5pt}
\begin{longtable}{c cr c crrcc cc rSc c}
    \caption{Summary of stuff.}
    \label{tab:big_table_over_margins}\\
    \toprule
\thead{Work}    &   \mc{2}{Parallelism} &   \mc{1}{Data}
    &   \mc{5}{LDPC Code}   &   \mc{2}{Decoding}
        &   \mc{3}{Perf.}   &   \mc{1}{Platform}    \\
    \cmidrule(r){1-1}\cmidrule(lr){2-3}\cmidrule(lr){4-4}
        \cmidrule(lr){5-9}\cmidrule(lr){10-11}\cmidrule(lr){12-14}
            \cmidrule(l){15-15}
    &   \mc{1}{Thread}  &   \mc{1}{Data}    &   \mc{1}{Width}
        &   \mc{1}{Code}    &   \mc{1}{q}   &   \mc{1}{N}   &   \mc{1}{Rate}
            &   \mc{1}{Tanner}  &   \mc{1}{Sched.}  &   \mc{1}{Alg.}
                &   \thead{Lat.\\(ms)}  &   {\thead{Thr.\\(Mbit/s)}}
                    &   \mc{1}{Iter.}   &   \mc{1}{Name}  \\
    \midrule
%
\mrc{5}{Work 1} & \mrc{5}{bpc} & \mrcR{3}{512} & \mrc{5}{6--8} & \mrc{5}{802.16e} & \mrcR{5}{2} & 768 & \mrc{5}{1/2} & \mrc{5}{Struct.} & \mrc{5}{TDMP} & \mrc{5}{MSA} & 2.62 & 150 & \mrc{5}{10} & \mrc{5}{GeForce\\9800 GTX+}
        \\
 &  &     &  &  &  & 1152 &  &  &  &  & 3.88  & 152 &  & \\
 &  &     &  &  &  & 1536 &  &  &  &  & 4.91  & 160 &  & \\
 &  & 384 &  &  &  & 1920 &  &  &  &  & 5.27  & 140 &  & \\
 &  & 256 &  &  &  & 2304 &  &  &  &  & 3.69  & 160 &  & \\
Work 2 & {cpc} & 128 & 8 & 802.16e & 2 & 2304 & 1/2 & Struct. & TDMP & MSA & 1.09 & 270 & 10 & \thead{Cell\\B.E.}
        \\
    \midrule
 \mrc{4}{Work 3} & \mrc{4}{tpn} & \mrcR{4}{1} & \mrc{4}{8} & \mrc{4}{802.16e}
    &  & 768 & \mrc{4}{xxx} & \mrc{4}{Struct.} & \mrc{4}{TPMP} & \mrc{4}{MSA}
        & 0.01 & 98.7 & \mrc{4}{10} & \mrc{4}{Nallatech\\PCI 385N D5} \\
  &  &  &  &  &  & 1152 &  &  &  &  & 0.01 & 103.9 &  & \\
  &  &  &  &  &  & 1536 &  &  &  &  & 0.02 & 81.4  &  & \\
  &  &  &  &  &  & 1920 &  &  &  &  & 0.02 & 81.0  &  & \\
 \mrc{4}{Work 4} & \mrc{4}{bpe}  & \mrcR{4}{4} & \mrc{4}{32} & \mrc{4}{Regular} & 32 & \mrc{4}{384} & \mrc{4}{1/3} & \mrc{4}{Sparse} & \mrc{4}{TPMP} & \mrc{4}{FFT-\\-SPA} & 14.93 & 0.82 & \mrc{4}{10} & \mrc{4}{Tesla\\C1060}
        \\
  &  &  &  &  & 64  &  &  &  &  &  & 31.55 & 0.39 &  & \\
  &  &  &  &  & 128 &  &  &  &  &  & 7.36  & 1.67 &  & \\
  &  &  &  &  & 256 &  &  &  &  &  & 10.28 & 1.20 &  & \\
    \midrule
 \mrc{6}{Work 5} & \mrc{2}{tpn} & \mrcR{6}{1} & \mrc{6}{8} & \mrc{2}{802.11n} & \mrcR{6}{2} & \mrc{2}{1944} & \mrc{2}{1/2} & \mrc{2}{Struct.} & \mrc{2}{TPMP} & \mrc{2}{MSA} & 0.12 & 16 & \mrc{6}{10} & \mrc{2}{Nallatech\\PCI 385N D5}
        \\
  &  &  &  &  &  &  &  &  &  &  & 0.09 & 21 &  & \\
  & \mrc{4}{N/A} &  &  & \mrc{4}{DVB-S2} &  & \mrc{4}{64800} & \mrc{4}{1/2} & \mrc{4}{Struct.} & \mrc{4}{TPMP\\TDMP} & \mrc{4}{MSA} & 0.28 & 234 &  & \mrc{2}{Virtex5 LX330T\\Max2 Board}
        \\
  &  &  &  &  &  &  &  &  &  &  & 0.05 & 1260 &  &
        \\
  &  &  &  &  &  &  &  &  &  &  & 0.28 & 234 &  & \mrc{2}{Virtex6 LX330T\\Max3 Boar}
        \\
  &  &  &  &  &  &  &  &  &  &  & 0.05 & 1296 &  & \\
 \bottomrule
\end{longtable}
\lipsum[1]
    \end{document}

Similarly you can improve other your tables. And on the end, with package showframe you can see if the table fit the text width.

  • Thanks for the solution closer to what I want, and for the reworking of the table style. It looks better now. However, notice that when the entry at the third column (Parallelism>Data) first row (spanning three rows) with the source \mrc{3}{512}. It aligns differently than 384 immediately below. Can this be fixed. From what I read in the package documentation only \raggedright is defined under multirow. – Joao Andrade Oct 8 '15 at 0:02
  • @JoaoAndrade, I see. For other align than right you need add options for vertical and horizontal alignment, for example mrc{3}[0pt][c]{512}. If all multi row cells should have centered content, than just redefine \mrc into \newcommand\mrc[2]{\multirowcell{#1}[0pt][c]{#2}}. – Zarko Oct 8 '15 at 0:32
  • @JoaoAndrade, I reformat your table again, hopefully now it fulfill your wishes. – Zarko Oct 8 '15 at 10:49
  • I saw it in the morning, only now I have the chance to acknowledge it. – Joao Andrade Oct 8 '15 at 16:10

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.