Is it possible to use vhdl in LaTeX code to get block diagrams?

% ...
% entity Comp is generic ( n : natural := 2 );
% port (
%    A       : in std_logic_vector(n-1 downto 0);
%    B       : in std_logic_vector(n-1 downto 0);
%    greater : out std_logic;
%    less    : out std_logic;
%    equal   : out std_logic;
%end Comp;

Result like here: http://vhdltolatex.mamikon.net/

How can I define block diagrams without telling the position of the elements? I would like an automatical layout.


I don't know vhdl, hence I'm not sure this is an answer your question.

If you want to change the diagram because you have more/less element before or after the item node, you have only to add/remove elements from the left/right matrices, change the factor who divide \myheight and adjust the \foreach conditions.

\usetikzlibrary{matrix, positioning, arrows.meta}
    circuit/.style={draw,minimum width=2cm,minimum height=\myheight,very thick,inner sep=1mm,outer sep=0pt,cap=round,font=\sffamily\bfseries},
    triangle 45/.tip={Triangle[angle=45:8pt]}

        \begin{tikzpicture}[font=\sffamily,>=triangle 45]
        \node [circuit] (item) {Comp};
            matrix of nodes, 
            left= of item, 
            row sep=\myheight/5,
            ] (rightmatr) { 
            matrix of nodes, 
            right= of item, 
            row sep=\myheight/6,
            ] (leftmatr) { 
        \foreach \i in {1,2}
            \draw [->] (rightmatr-\i-1) -- (rightmatr-\i-1 -| item.west);
        \foreach \i in {1,2,3}
            \draw [<-] (leftmatr-\i-1) -- (leftmatr-\i-1 -| item.east);
        \caption{Entity of Comp}

enter image description here

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