1

Consider the following trivial code:

\documentclass{standalone}

\usepackage{tikz}
\usetikzlibrary{calc, shapes.gates.logic.US}

\begin{document}
  \begin{tikzpicture}
    \node[or gate US, draw, logic gate inputs=nnn, line width=0.8pt] (OR1) at (2.5, 0) {};
    \draw (OR1.input 1) |- ++(-1, 0) {};
    \draw (OR1.input 3) |- ++(-1, 0) {};
    \draw (OR1.output) |- ++(+1, 0) {};
  \end{tikzpicture}
\end{document}

This produces the following output:

enter image description here

As you can see (especially if you zoom in), the wires clearly don't touch the logic gate! :-O The output wire has the move obvious gap, but both input wires also have small gaps too.

This is extremely annoying! Why is it doing this?! Why is such obviously broken behavior the default?

It seems the effect is only visible with the OR gate (presumably because all the other types of gate just happen to have exactly vertical lines where the wires join).

How can I get rid of this abhorrent misdrawing? So far, the only thing I can come up with is

\begin{tikzpicture}
  \node[or gate US, draw, logic gate inputs=nnn, line width=0.8pt] (OR1) at (2.5, 0) {};
  \draw ($(OR1.input 1)+(0.01, 0)$) |- ++(-1, 0) {};
  \draw ($(OR1.input 3)+(0.01, 0)$) |- ++(-1, 0) {};
  \draw ($(OR1.output)+(-0.01, 0)$) |- ++(+1, 0) {};
\end{tikzpicture}

With this modification, the picture now draws correctly. That's a hell of a lot of extra typing, though. [For every single OR gate in every circuit, ever.] Is there really no way to fix this permanently? (I'm still not sure why it even needs fixing in the first place... Has nobody ever used this library or something?)

1
  • I believe pointy or gates are relatively new, and no one else has noticed the gap. Not too long ago logic gate didn't even use \pgfpathclose around the borders. – John Kormylo May 24 '20 at 12:39
2

Try add outer sep=0pt to or gate US node's options:

\documentclass[tikz, matgin=3mm]{standalone}
\usetikzlibrary{shapes.gates.logic.US}

\begin{document}
  \begin{tikzpicture}
            \node[or gate US, draw, logic gate inputs=nnn, line width=0.8pt,
                  outer sep=0pt]    % <---
          (OR1) at (2.5, 0) {};
    \draw (OR1.input 1) |- ++(-1, 0) {};
    \draw (OR1.input 3) |- ++(-1, 0) {};
    \draw (OR1.output) |- ++(+1, 0) {};
  \end{tikzpicture}
\end{document}

enter image description here

Adendum:

With circuitikz package is simpler:

\documentclass[ margin=3mm]{standalone}
\usepackage{circuitikz}

\begin{document}
  \begin{circuitikz}
  \ctikzset{logic ports=ieee}
\node[ieeestd or port]   (OR1) at (2.5, 0) {};
    \draw (OR1.bin 1) |- ++(-1, 0) {};
    \draw (OR1.bin 2) |- ++(-1, 0) {};
    \draw (OR1.bout)  |- ++(+1, 0) {};
  \end{circuitikz}
\end{document}

enter image description here

2
  • Outstanding! Thank you. – MathematicalOrchid May 24 '20 at 11:42
  • 1
    You are welcome! See addendum to my answer, you might liked it. Also you may consider to accept my answer :-) – Zarko May 24 '20 at 11:54

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