The standard dimensions of components are chosen so that the distance between the inputs of a logic port is the same as the distance between chip pins. So you really need to scale one or another.
The safest way to scale a component is using its class options (see section 3.3 and following in the manual); the same for the line thickness. I used a global option for the thickness and a local one for the scale to show the two possibilities.
For the pin numbers, you can decide to hide them and add them manually do you can do whatever you like with them.
Example:
\documentclass[border=10pt]{standalone}
\usepackage[siunitx, RPvoltages]{circuitikz}
\begin{document}
\ctikzset{
logic ports=ieee,
logic ports origin=center, % not needed for IEEE
chips/thickness=4,
}
\begin{tikzpicture}
% when using in a node, you have to prepend "circuitikz/"
\node[dipchip, num pins=16, hide numbers, circuitikz/chips/scale=2](C){};
% put the nand port: horizontally midway between pin 6 and 7
% vertically in the center of the chip
\path ($(C.bpin 6)!0.5!(C.bpin 7)$) coordinate (midway-6-7)
(midway-6-7 -| C.north) node[nand port](N1){};
% connect pins
\draw (C.bpin 6) -| (N1.in 1);
\draw (C.bpin 7) -| (N1.in 2);
\draw (C.bpin 9) -| (N1.out);
% external numbers
\foreach \pin in {1,...,8} \node[font=\tiny, above left] at(C.bpin \pin) {\pin};
\foreach \pin in {9,...,16} \node[font=\tiny, above right] at(C.bpin \pin) {\pin};
\end{tikzpicture}
\end{document}